Dynamic random access memory (DRAM) devices provide the benefits of higher storage densities and less power consumption in comparison to other memory technologies, including and most notably, static random access memory (SRAM) devices. However, these benefits come at the cost of incurring various delays in accessing the memory cells making up a DRAM device, both at regular intervals, and in the time periods immediately before and after each access to either read data from the memory cells or to write data to the memory cells.
As is well known to those skilled in the art, these myriad delays arise from the dynamic nature of the storage of data that gives DRAM devices their name. Each memory cell is made up of transistors configured to function very much like a capacitor that stores the binary 0 or 1 representing a bit of data as a charge. This capacitor-like configuration of transistors requires fewer transistors and less power than does a memory cell of a SRAM device, making possible the higher densities and lower power consumption of DRAM devices. However, this same capacitor-like configuration of transistors leaks the charge over time, allowing the charge to decay over time, and resulting in the need to carry out refresh operations to restore the charge at regular intervals. This same capacitor-like configuration also entirely loses its charge (i.e., literally discharges) when the charge representing the binary 0 or 1 is read from the memory cell, thereby requiring subsequent operations to be carried out to restore the charge representing the binary 0 or 1 that was just read. Furthermore, due to the minute amplitude and transitory lifespan of the discharged charges received from the memory cells when the binary 0 or 1 values are read, sense amplifiers are needed to both amplify and latch the discharged charges received from the memory cells. This same minute amplitude also requires that the conductors carrying the discharged charges from the memory cells to corresponding sense amplifiers be precharged to a voltage level that will not mask or overwhelm the discharged charges such that the sense amplifiers are prevented from accurately receiving and latching the binary 0 and 1 values read from the memory cells.
It is the refresh operations to maintain the charge stored in each memory cell, the operations to restore charges lost in discharging for a read operation, and the operations to precharge conductors for carrying the discharged charges, as well as other maintenance operations, that impose the various delays that are suffered as a result of employing DRAM technology. These delays have the effect of limiting the rate at which data may be written to or read from DRAM devices, and although components such as processors have made great strides in becoming ever faster, comparatively little progress has been made in increasing the rate of reading data from and writing data to these capacitor-like memory cells.
Various techniques have been devised to “hide” this growing disparity in speed between processors and DRAM memory devices, including the use of SRAM devices as caches and interleaving accesses made to different DRAM devices out of a grouping of multiple DRAM devices. However, the addition of SRAM devices to serve as a cache frequently adds many more components (thereby increasing costs) and a considerable increase in the amount of power used. Also, the interleaving of accesses to multiple DRAM devices adds considerable complexity and often a need for wider memory buses to a memory system made up of DRAM devices. Some other way of counteracting the effects of the disparity in speed between processors and DRAM devices that does not suffer these drawbacks would be desirable.